Late-stage FPGA timing closure often starts from an implemented design whose remaining violations are visible in timing reports. Engineering change order (ECO) optimization is a standard mechanism for applying localized changes to such designs without restarting the full implementation flow. Automating post-route ECO optimization remains challenging. A post-route change must improve timing without violating routing legality, hold or pulse-width timing constraints, checkpoint replayability or functional equivalence.

This paper presents PACT, a Post-route Agentic Checkpoint Tuning framework for Vivado design checkpoints (DCP). PACT represents post-route tuning as validation-gated transitions between accepted and candidate checkpoints. From checkpoint-derived evidence, an agent selects localized backend actions through a profile-driven recipe planner over typed Vivado and RapidWright skills, and probes tool behavior in isolated workspaces. PACT records each trial as an evidence-gated case to guide candidate generation and suppress unsafe, unsupported or ineffective actions.

Across 35 UltraScale+ post-route checkpoints, PACT improves validation-clean Fmax (maximum operating frequency) by a geometric mean of +22.30% over the original implementations, compared with +15.14% for DATuner and +9.78% for the Codex Agent. On shared designs, PACT achieves these gains 6.4× faster than the uncapped DATuner and at an average token cost of only $0.16 per DCP (24.5× lower than the free-form Codex Agent).

正文为论文摘要原文，数学记号已转为纯文本。

@misc{lin2026pactpostrouteagenticcheckpoint,
      title={PACT: Post-route Agentic Checkpoint Tuning for FPGA Timing Closure},
      author={Huan Lin and Kunlong Li and Lingli Wang and Zhiang Wang},
      year={2026},
      eprint={2608.23602},
      archivePrefix={arXiv},
      primaryClass={cs.AR},
      url={https://arxiv.org/abs/2608.23602},
}