Huan Lin

A multi-protocol LLM API gateway written in Rust, speaking OpenAI / Anthropic / Gemini

RustAxumTokioSeaORMWASM

Repository

An agentic post-route timing optimiser for FPGAs, with the design checkpoint as its state

PythonVivadoRapidWrightLLM Agent

Repository

• Treated the Vivado design checkpoint as the optimisation state: localised ECOs planned from physical-design evidence, every candidate gated on legality and timing, with rollback and recording.
• Wrapped Vivado and RapidWright into typed actions — critical-net rerouting, driver replication, local replacement, logic restructuring, region constraints, global fallback.
• Across 35 UltraScale+ checkpoints: +22.30% geometric-mean Fmax, versus 15.14% for DATuner and 9.78% for a general-purpose Codex agent; 6.4× faster than DATuner at $0.16 per DCP, 24.5× cheaper.

• Accelerated three Chinese post-quantum KEMs — Aigis-1024, PolarLAC-256 and Scloud+-256 — on one shared reconfigurable CGRA: hardware/software partitioning from per-function cycle profiles, 26 C kernels mapped into 75 CGRA configurations covering NTT, polynomial and matrix multiply, and packing.
• Tuned the array and runtime for KEMs — NTT resident on chip across all seven stages (Aigis decaps 252k → 130k cycles), whole task chains submitted to a hardware queue, shared Keccak units, Scloud+'s 1184×1184 matrix generated row by row instead of stored (2.8 MB saved; per-request CPU work from ~300M to under 0.5M cycles), and eight interleaved request contexts.
• In cycle-accurate RTL simulation of the full SoC (Rocket CPU + 8×32 CGRA), all three algorithms meet the single-engine target for keygen, encaps and decaps (Aigis 5000 / PolarLAC 4000 / Scloud+ 1000 ops/s); decaps reaches 5583 / 4289 / 1025 ops/s, byte-exact against the reference implementations.
• 40 nm LP synthesis (pre-layout): 346 → 499.75 MHz by cutting critical paths, array power 2.53 → 0.89 W with clock gating; 16.3 mm² of CGRA versus 21.0 mm² for three dedicated HLS ASICs, about 22% smaller.

• Extended a spatial CGRA into a multi-context temporal architecture, reworking the LLVM compiler, hardware generator and mapper together, with spatio-temporal reuse of the configuration and cache register files.
• Found that functionally equivalent DFGs with identical compute and I/O node counts can still differ markedly in throughput, purely because of their connection structure.
• Built mapping-driven compiler optimisation that traces routing conflicts and congestion back to the DFG and picks semantics-preserving graph transformations to lower II and raise mapping success.

• Built an LLVM source-to-source plugin that flattens directly recursive functions into iterative form, compatible with Bambu HLS.
• Kept the design modular, leaving hooks for indirect recursion and more complex call graphs; validated as a prototype.

• Benchmarked the team's existing performance-analysis framework, then led a next-generation analytical estimator to replace it — first end-to-end on DeepSeek V4-Pro, then across several major model families, with results aligned to the original framework.
• Calibrated model configs, operator characteristics and execution behaviour from model datasheets; added DDR/SSD second-tier buffer performance and capacity modelling, concurrent inference, prefix caching and expert-weight offloading, analysing TTFT, TPOT, memory and throughput across prefill and decode.
• Shipped a visual web interface and offline deployment so the team uses it for design comparison and capacity planning. Mentor's overall rating — Excellent.

• Designed a programmable vector unit around an internal special-function IP, carrying the CGRA's configurable routing and configuration registers over to the vector datapath so that many special functions share one runtime-configured unit.
• Worked on NPU runtime bring-up and instruction interfaces — instruction definitions, call constraints, validation cases — and packaged the repetitive debug flow into an LLM skill.

• Placed 4th of 66 teams in the post-route FPGA optimisation track, with a cash prize.
• Positive Fmax improvement on all 7 benchmarks, averaging 56.1 MHz and peaking at 85.4 MHz.

• Presenting PACT at FPT 2026. The paper site collects the method, per-design results on all 35 checkpoints, slides and the reproducible artifact.

• Co-organised an FPT 2025 workshop on an open-source reconfigurable SoC framework spanning MLIR/LLVM front-end compilation to ASIC implementation; built the workshop site and the Chipyard hands-on tutorial.