Huan Lin

A multi-protocol LLM API gateway written in Rust, speaking OpenAI / Anthropic / Gemini

RustAxumTokioSeaORMWASM

Repository

An agentic post-route timing optimiser for FPGAs, with the design checkpoint as its state

PythonVivadoRapidWrightLLM Agent

Repository

• Traced routing feedback — unrouted edges, contended links and GIBs, congestion, fan-out, reconvergence — back to specific DFG nodes and edges, feeding an agent that applies semantics-preserving transformations.
• Designed the transformations themselves — reordering commutative stages, restructuring boundary connectivity — evaluating placement, scheduling and routing jointly to lower II and raise success rates at high utilisation.

• Led CGRA acceleration of post-quantum cryptography: from RISC-V reference implementations through algorithm decomposition, operator and DFG extraction, and bottleneck analysis to architectural requirements.
• Decomposed the throughput and cycle budget against a 1 Kcps single-engine target, across compute parallelism, memory bandwidth, interconnect traffic and mapping II.
• Mapped and evaluated the core compute stages under an idealised CPU–CGRA split, simulating roughly 1.1 Kcps. Automatic region identification and co-compilation are in progress.

• Treated the Vivado design checkpoint as the optimisation state: localised ECOs planned from physical-design evidence, every candidate gated on legality and timing, with rollback and recording.
• Wrapped Vivado and RapidWright into typed actions — critical-net rerouting, driver replication, local replacement, logic restructuring, region constraints, global fallback.
• Across 35 UltraScale+ checkpoints: +22.30% geometric-mean Fmax, versus 15.14% for DATuner and 9.78% for a general-purpose Codex agent; 6.4× faster than DATuner at $0.16 per DCP, 24.5× cheaper.

• Extended a spatial-CGRA LLVM compiler, hardware generator and mapper to also cover multi-context temporal CGRAs under one DFG and mapping flow, with spatio-temporal reuse of the configuration and cache register files.
• Found that functionally equivalent DFGs with identical compute and I/O node counts can still differ markedly in throughput, purely because of their connection structure.
• Designed semantics-preserving graph transformations that exploit this: some previously unmappable DFGs become mappable without changing the architecture, and II drops on some mappable cases.

• Built an LLVM source-to-source plugin that flattens directly recursive functions into iterative form, compatible with Bambu HLS.
• Kept the design modular, leaving hooks for indirect recursion and more complex call graphs; validated as a prototype.

• Adapted and maintained model support in an LLM inference performance estimation framework, wiring in computation graphs, operator characteristics, and hardware compute, bandwidth and memory configs.
• Mapped prefill and decode onto the operator- and phase-level models, analysing TTFT, TPOT and memory across batch size, sequence length, KV cache length and parallelism.
• Aligned predictions against the internal framework and extended the model to concurrent inference, for latency and throughput under multi-request load.

• Characterised a proprietary SFU — compute semantics, datapath interfaces, instruction granularity, call paths — to pin down the constraints for integrating a reconfigurable vector unit.
• Worked on the interface between the vector unit and the software runtime, extending NPU instruction definitions, call constraints, and validation cases.
• Diagnosed instruction-semantics, data-format and boundary-condition issues during bring-up, then packaged the repetitive debug and validation steps into an LLM skill.

• Finished in the top 5 of the post-route FPGA optimisation track and received a cash prize; final placement to be announced at FPL 2026.
• Positive Fmax improvement on all 7 benchmarks, averaging 56.1 MHz and peaking at 85.4 MHz.