PACT
2026-03 – 2026-06An agentic post-route timing optimiser for FPGAs, with the design checkpoint as its state
PythonVivadoRapidWrightLLM Agent
The engineering behind the paper accepted at FPT 2026. See the paper page.
The same approach was entered into the FPL 2026 Optimization Contest, placing 4th of 66 in the post-route FPGA optimisation track with a cash prize: positive Fmax improvement on all 7 benchmarks, averaging 56.1 MHz and peaking at 85.4 MHz.